HP EZ-KIT Manuel d'utilisateur télécharger pdf (Page 78)

Example 6: Project Options

5-6 Getting Started with ADSP-BF548 EZ-KIT Lite

the application’s general performance. The processor’s caches or memory

protection features require a control table, the cacheability and protection

lookaside buffer (CPLB), to be set up. Typically this is done automatically

by VisualDSP++ using appropriate default settings. However, current FSS

and some device drivers cannot operate correctly when the data sections

they read to or write from are cacheable. To allow this, the option Gener-

ate a customizable CPLB table has been selected (in the lower half of the

Cache and Memory Protection window). The option provides the oppor-

tunity to modify the appropriate CPLB table entries.

When you finish browsing the project options, click Cancel rather than

OK to dismiss the dialog box in case you unintentionally modified any

project settings.

Figure 5-2. User Heap Settings

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HP EZ-KIT Manuel d'utilisateur Page 78