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Electrical Specifications

34 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

leak-

High impedance leakage to GND N/A 10 µA

bus

Bus capacitance per node N/A 10 pF

noise

Signal noise immunity above 300 MHz 0.1 * V

—V

p-p

Notes:

supplies the PECI interface. PECI behavior does not affect V

min/max specifications. Refer

Table 2-3 for V

specifications.

2. The input buffers use a Schmitt-triggered input design for improved noise immunity.

3. The leakage specification applies to powered devices on the PECI bus.

4. One node is counted for each client and one node for the system host. Extended trace lengths

might appear as additional nodes.

Table 20. PECI DC Electrical Limits

Symbol Definition and Conditions Min Max Units Notes

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 101 102

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