HP AT80613003543AF Fiche technique Page 47
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Land Listing and Signal Descriptions
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 49
D24# F12 Source Synch Input/Output
D25# D13 Source Synch Input/Output
D26# E13 Source Synch Input/Output
D27# G13 Source Synch Input/Output
D28# F14 Source Synch Input/Output
D29# G14 Source Synch Input/Output
D30# F15 Source Synch Input/Output
D31# G15 Source Synch Input/Output
D32# G16 Source Synch Input/Output
D33# E15 Source Synch Input/Output
D34# E16 Source Synch Input/Output
D35# G18 Source Synch Input/Output
D36# G17 Source Synch Input/Output
D37# F17 Source Synch Input/Output
D38# F18 Source Synch Input/Output
D39# E18 Source Synch Input/Output
D40# E19 Source Synch Input/Output
D41# F20 Source Synch Input/Output
D42# E21 Source Synch Input/Output
D43# F21 Source Synch Input/Output
D44# G21 Source Synch Input/Output
D45# E22 Source Synch Input/Output
D46# D22 Source Synch Input/Output
D47# G22 Source Synch Input/Output
D48# D20 Source Synch Input/Output
D49# D17 Source Synch Input/Output
D50# A14 Source Synch Input/Output
D51# C15 Source Synch Input/Output
D52# C14 Source Synch Input/Output
D53# B15 Source Synch Input/Output
D54# C18 Source Synch Input/Output
D55# B16 Source Synch Input/Output
D56# A17 Source Synch Input/Output
D57# B18 Source Synch Input/Output
D58# C21 Source Synch Input/Output
D59# B21 Source Synch Input/Output
D60# B19 Source Synch Input/Output
D61# A19 Source Synch Input/Output
D62# A22 Source Synch Input/Output
D63# B22 Source Synch Input/Output
Table 4-1. Alphabetical Land
Assignments (Sheet 3 of 20)
Land Name Land #
Signal Buffer
Type
Direction
DBI0# A8 Source Synch Input/Output
DBI1# G11 Source Synch Input/Output
DBI2# D19 Source Synch Input/Output
DBI3# C20 Source Synch Input/Output
DBR# AC2 Power/Other Output
DBSY# B2 Common Clock Input/Output
DEFER# G7 Common Clock Input
DRDY# C1 Common Clock Input/Output
DSTBN0# C8 Source Synch Input/Output
DSTBN1# G12 Source Synch Input/Output
DSTBN2# G20 Source Synch Input/Output
DSTBN3# A16 Source Synch Input/Output
DSTBP0# B9 Source Synch Input/Output
DSTBP1# E12 Source Synch Input/Output
DSTBP2# G19 Source Synch Input/Output
DSTBP3# C17 Source Synch Input/Output
FC0 Y1 Power/Other
FC3 J2 Power/Other
FC4 T2 Power/Other
FC5 F2 Power/Other
FC8 AK6 Power/Other
FC10 E24 Power/Other
FC15 H29 Power/Other
FC17 Y3 Power/Other
FC18 AE3 Power/Other
FC20 E5 Power/Other
FC21 F6 Power/Other
FC22 J3 Power/Other
FC23 A24 Power/Other
FC26 E29 Power/Other
FC27 G1 Power/Other
FC28 U1 Power/Other
FC29 U2 Power/Other
FC30 U3 Power/Other
FC31 J16 Power/Other
FC32 H15 Power/Other
FC33 H16 Power/Other
FC34 J17 Power/Other
FC35 H4 Power/Other
FC36 AD3 Power/Other
Table 4-1. Alphabetical Land
Assignments (Sheet 4 of 20)
Land Name Land #
Signal Buffer
Type
Direction
- Dual-Core Intel 1
- Processor 1
- Contents 3
- 1, 2, 3, 4 6
- Revision History 7
- 3000 Series Features 8
- 1 Introduction 9
- 1.1.1 Processor Terminology 10
- 1.2 References 11
- 1, 2, 5 12
- 2 Electrical Specifications 13
- 2.3 Voltage Identification 14
- Electrical Specifications 17
- Table 2-5. V 19
- Figure 2-1. V 20
- Table 2-6. V 20
- (Sheet 1 of 2) 20
- (Sheet 2 of 2) 21
- Figure 2-2. V 21
- Overshoot 22
- 2.6.4 Die Voltage Validation 22
- 2.7 Signaling Specifications 23
- 2.7.4 Clock Specifications 27
- 2.8 PECI DC Specifications 31
- Table 2-3 for V 32
- 3 Package Mechanical 33
- 3.2 Processor Markings 39
- INTEL ©'05 3065 40
- INTEL® XEON® 40
- SLxxx [COO] 40
- 2.33GHZ/4M/1333/06 40
- Preliminary 41
- Socket 775 41
- Quadrants 41
- Top View 41
- 4 Land Listing and Signal 43
- Descriptions 43
- Table 4-1. Alphabetical Land 46
- Assignments (Sheet 1 of 20) 46
- Assignments (Sheet 2 of 20) 46
- Assignments (Sheet 3 of 20) 47
- Assignments (Sheet 4 of 20) 47
- Assignments (Sheet 5 of 20) 48
- Assignments (Sheet 6 of 20) 48
- Assignments (Sheet 7 of 20) 49
- Assignments (Sheet 8 of 20) 49
- Assignments (Sheet 9 of 20) 50
- Assignments (Sheet 10 of 20) 50
- Assignments (Sheet 11 of 20) 51
- Assignments (Sheet 12 of 20) 51
- Assignments (Sheet 13 of 20) 52
- Assignments (Sheet 14 of 20) 52
- Assignments (Sheet 15 of 20) 53
- Assignments (Sheet 16 of 20) 53
- Assignments (Sheet 17 of 20) 54
- Assignments (Sheet 18 of 20) 54
- Assignments (Sheet 19 of 20) 55
- Assignments (Sheet 20 of 20) 55
- (Sheet 1 of 20) 56
- (Sheet 2 of 20) 56
- (Sheet 3 of 20) 57
- (Sheet 4 of 20) 57
- (Sheet 5 of 20) 58
- (Sheet 6 of 20) 58
- (Sheet 7 of 20) 59
- (Sheet 8 of 20) 59
- (Sheet 9 of 20) 60
- (Sheet 10 of 20) 60
- (Sheet 11 of 20) 61
- (Sheet 12 of 20) 61
- (Sheet 13 of 20) 62
- (Sheet 14 of 20) 62
- (Sheet 15 of 20) 63
- (Sheet 16 of 20) 63
- (Sheet 17 of 20) 64
- (Sheet 18 of 20) 64
- (Sheet 19 of 20) 65
- (Sheet 20 of 20) 65
- 5 Thermal Specifications and 73
- Design Considerations 73
- 5.1.2 Thermal Metrology 78
- 5.2.1 Thermal Monitor 78
- 5.2.2 Thermal Monitor 2 79
- 5.3 Thermal Diode 81
- PECI Host 84
- Controller 84
- Domain 0 84
- 5.4.2.1 PECI Device Address 86
- 5.4.2.2 PECI Command Support 86
- 6 Features 87
- 6.2.2.1 HALT Powerdown State 88
- 6.2.3.1 Stop Grant State 89
- Features 90
- 6.3 Enhanced Intel 91
- SpeedStep 91
- Technology 91
- 7.1 Mechanical Specifications 94
- 7.2 Electrical Requirements 95
- 7.3 Thermal Specifications 97
- 7.3.2 Variable Speed Fan 99
- 8 Debug Tools Specifications 101
- Debug Tools Specifications 102
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