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UG471 (v1.5) May 15, 2015

IO_FIFO Overview

Clock Event 2

The data bit E appears at OQ one CLK cycle after EFGH is sampled into the OSERDESE2.

This latency is consistent with the Table 3-11 listing of a 4:1 DDR mode OSERDESE2

latency of one CLK cycle.

The 3-state bit 0 at T1 during Clock Event 1 appears at TQ one CLK cycle after 0010 is

sampled into the OSERDESE2 3-state block. This latency is consistent with the Table 3-11

listing of a 4:1 DDR mode OSERDESE2 latency of one CLK cycle.

OSERDESE2 VHDL and Verilog Instantiation Templates

The Libraries Guide includes instantiation templates of the OSERDESE2 module in VHDL

and Verilog.

IO_FIFO Overview

7 series devices have shallow IN_FIFOs and OUT_FIFOs (called IO_FIFOs collectively)

located in each of the I/O banks. Although these IO_FIFOs are specifically designed for

memory applications, they are available as general resources. For general use, all inputs

and outputs are routed via interconnect. The most common use of IO_FIFOs is to interface

with external components as an extension of IOLOGIC (e.g., ISERDES or IDDR and

OSERDES or ODDR). Because of their general interconnect capability, IO_FIFOs can also

serve as additional fabric FIFO resources.

Each I/O bank contains four IO_FIFOs with one IO_FIFO per byte group. A byte group is

defined as 12 I/Os within a bank. The IO_FIFOs are physically aligned to an I/O byte

group. This alignment yields the best performance when IO_FIFOs are used to interface to

IOI components such as the input and output SERDES elements, which is their most

common use. However, regardless of their location, IO_FIFOs can also interface to

resources in the FPGA fabric and other I/O banks (see UG475

, 7 Series FPGAs Packaging and

Pinout Specifications for byte group pin arrangements). This section focuses on the use of

IO_FIFOs to interface with IOI components.

For external data flowing into the FPGA, an IN_FIFO can connect to the ILOGIC (e.g.,

ISERDESE2, IDDR, or IBUF) to receive incoming data and pass it on to the fabric. For data

flowing out of the FPGA, an OUT_FIFO can connect to the OLOGIC (e.g., OSERDESE2,

ODDR, or OBUF) to pass data from the fabric and send it through to the IOB.

An IN_FIFO receives 4-bit data from an ILOGIC block while the fabric side reads either 4-

or 8- bit data out of the array. An OUT_FIFO receives 4- or 8- bit data from the fabric while

an OLOGIC block reads 4-bit data out of the array.

Each IO_FIFO has a 768-bit storage array and can be arranged as twelve groups of 4-bit

data or ten groups of 8-bit data. An IO_FIFO is nine entries deep, including an input and

output register. Typical IO_FIFO uses are as a buffer for a parallel I/O interface crossing

between two frequency domains (e.g., the BUFR domain to/from the BUFG or BUFH

domain) or as a 2:1 serializer/deserializer to decouple the PHY from the fabric to relax

fabric performance requirements.

IO_FIFOs are shallower versions of regular FIFOs and have similar functionality. The

primary purpose of IO_FIFOs is to support I/O data transfer functions. They are not

intended to replace built-in FIFOs or LUT-based FIFOs. IO_FIFOs support standard flag

logic, clocks, and control signals. IO_FIFOs can operate in two modes, 4 x 4 mode (1:1) or

4x8/8x4 mode (1:2/2:1).

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