7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 97
UG471 (v1.5) May 15, 2015
Rules for Combining I/O Standards in the Same Bank
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different input, output, and bidirectional
standards in the same bank:
1. Combining output standards only. Output standards with the same output V
CCO
requirement can be combined in the same bank.
Compatible example:
SSTL15_I and LVDCI_15 outputs
Incompatible example:
SSTL15 (output V
CCO
= 1.5V) and
LVCMOS18 (output V
CCO
= 1.8V) outputs
2. Combining input standards only. Input standards with the same V
CCO
and V
REF
requirements can be combined in the same bank.
Compatible example:
LVCMOS15 and HSTL_II inputs
Incompatible example:
LVCMOS15 (input V
CCO
= 1.5V) and
LVCMOS18 (input V
CCO
= 1.8V) inputs
Incompatible example:
HSTL_I_DCI_18 (V
REF
= 0.9V) and
HSTL_I_DCI (V
REF
= 0.75V) inputs
3. Combining input standards and output standards. Input standards and output
standards with the same V
CCO
requirement can be combined in the same bank.
Compatible example:
LVDS_25 output and LVCMOS25 input
Incompatible example:
LVDS_25 output (output V
CCO
= 2.5V) and
HSTL_I_DCI_18 input (input V
CCO
= 1.8V)
4. Combining bidirectional standards with input or output standards. When
combining bidirectional I/O with other standards, make sure the bidirectional
standard can meet the first three rules.
5. Additional rules for combining DCI I/O standards.
a. Only one DCI target resistance value (controlled driver output impedance or split
termination) can be used in any one HP I/O bank (or group of banks when using
DCI chaining).
Incompatible example:
HSUL_12_DCI output with a 40Ω output impedance and SSTL12_T_DCI
input with 100Ω/100Ωm split termination
The implementation tools enforce these design rules.
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