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UG471 (v1.5) May 15, 2015

Input Serial-to-Parallel Logic Resources (ISERDESE2)

a shift right by one and shift left by three. In this example, on the eighth Bitslip operation,

the output pattern reverts to the initial pattern. This assumes that serial data is an eight bit

repeating pattern.

Although the repeating pattern seems to show that bitslip is a barrel shifting operation,

this is not the case. A bitslip operation adds one bit to the input data stream and loses the

nth bit in the input data stream. This causes the operation on repetitive patterns to appear

like a barrel shifter operation.

Guidelines for Using the Bitslip Submodule

In NETWORKING mode the Bitslip submodule is available. In all other modes, the

module is not available.

To invoke a Bitslip operation, the BITSLIP port must be asserted High for one CLKDIV

cycle. Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip must be

deasserted for at least one CLKDIV cycle between two Bitslip assertions. In both SDR and

DDR mode, the total latency from when the ISERDESE2 captures the asserted Bitslip input

to when the “bit-slipped” ISERDESE2 outputs Q1–Q8 are sampled into the FPGA logic by

CLKDIV is two CLKDIV cycles. From an applications perspective, a single Bitslip

command must be issued for one CLKDIV cycle only. From an applications perspective, a

single Bitslip command must be issued for one CLKDIV cycle only. The user logic should

wait for at least two CLKDIV cycles in SDR mode or three CLKDIV cycles in DDR mode,

before analyzing the received data pattern and potentially issuing another Bitslip

command. If the ISERDESE2 is reset, the Bitslip logic is also reset and returns back to its

initial state.

X-Ref Target - Figure 3-11

Figure 3-11: Bitslip Operation Examples

ug471_c3_11_012211

Bitslip

Operations

Executed

Output

Pattern (8:1)

00100111

01001110

10011100

00111001

01110010

11100100

11001001

10010011

Initial

Bitslip Operation in SDR Mode